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What voltage ranges are supported on Pentium® processors?
There are different voltage ranges required, depending upon which Pentium processor you have. The ranges are:

STD:	The VCC specification for the C2 and subsequent steppings of the Pentium processor
	is VCC = 3.135V to 3.6V. The voltage range for B-step parts remains at  3.135V–3.465V.  
	Note that all E0-step production parts are standard voltage.

VR:	This is a reduced voltage specification that has the range of 3.300V–3.465V.

VRE/MD:	These parts have a reduced and shifted voltage specification. The VRE voltage range for 
	the C2 and subsequent steppings of the Pentium processor is VCC = 3.40-3.60V.  
	The VRE voltage range for B-step parts remains at 3.45-3.60V. 

MD:	Standard voltage specification, but with reduced minimum valid timings.

If a processor package has this information, it will be on the bottom side following the s-spec marking. The notation will be a slash mark followed by ABC, such as SK110 / ABC.

Here is the decoding of ABC:

A)      S = standard voltage    (3.135 to 3.6V)
        V = VRE voltage         (3.4 to 3.6V)

B)      S = Part has standard timing specifications.
        M = Part has minimum valid MD timing specifications.

C)      S = Part has standard timing specifications
        U = Not tested for dual-processing operation, but  only for 
            uni-and multi-processing.

Use the s-specs shown in the following table to find the voltage requirements for your part.

Basic 75-,90-,100-,133-,150- 166, and 200 Mhz Pentium® Processor Identification Information
See the corresponding Note at the end of the table for items listing a number in the "Notes" column.

NOTES:

For a definition of STD, VR, VRE, MD, VRE/MD, see the answer to question # 10 above or  refer to 
Intel document 242480.
DP indicates that this part can only be used as a dual processor.  CPU Type 
of  "2"  or  "0 or 2"  indicates this part supports dual processing.

The Type corresponds to bits [13:12] of the EDX register after RESET, 
bits [13:12] of the EAX register after the CPUID instruction is 
executed. This is shown as 2 different values based on the operation of 
the device as the primary processor or the dual processor upgrade.

The Family corresponds to bits [11:8] of the EDX register after RESET, 
bits [11:8] of the EAX register after the CPUID instruction is executed.

The Model corresponds to bits [7:4] of the EDX register after RESET, 
bits [7:4] of the EAX register after the CPUID instruction is executed.

The Stepping corresponds to bits [3:0] of the EDX register after 
RESET, bits [3:0] of the EAX register after the CPUID instruction is 
executed.

1. TCASE = 60ÝC.
2. VRT  Intel's Voltage Reduction Technology: The VCC for I/O is 3.3V, 
   but the core VCC, accounting for about 90% of power usage, is reduced  
   to 2.9V, to reduce power consumption and heating.
3. No Kit   means that part meets the specifications but is not tested 
   to support 82498/82493 and 82497/82492 cache timings
4. STEPPING The cB1 stepping is logically equivalent to the C2-step, but 
   on a different manufacturing process.  The mcB1 step is logically 
   equivalent to the cB1 step  (except it does not support DP, APIC or  FRC).  
  The mcB1, mA1, mA4 and mcC0-steps also use Intel's VRT (Voltage 
   Reduction Technology, see note 2 above) and are available in the TCP and 
   SPGA package, primarily to support mobile applications.  All mobile  steppings 
   are distinguished by an additional "m" prefix, for "mobile".
5. This is a boxed Pentium processor without the attached fan heatsink.
6. This is a boxed Pentium processor with an attached fan heatsink.
7. These parts do not support boundary scan.  S106J was previously 
    marked  (and is the same as) SK106J.
8. DP, FRC and APIC features are not supported on these parts.
9. These parts are packaged in the Plastic Pin Grid Array (PPGA) 
   package.  For additional specifications of this package, see 
  Intel document 242480.